that barcelona AMD quad core is comming out monday!!! anyone going to get it???

I am definitely not getting it, I doubt it'll be cheaper than the Q6600, and we already now the cheapest is clocked on the same speed, but the Q6600 has four times the L2 cache, giving it the multi-tasking overhead. Plus, the Q6600 is one of the best overclockable processor that I know of.

lolz quad core. been there done that with Intel :]

I'll look at some of the reviews on how it stacks up against Intel quad cores but I doubt they will be able to hold their own even against the Q6600.

AMD quad core

"If you can't innovate, imitate."

Last time I checked, AMD's dont really depend on the L2 Cache, hence the 512kb and 1mb L2 caches.

Now lets see if this thing can possibly beat the C2D's

No, I will get it in a year or so when I upgrade my computer. But only because I am an AMD fan and just prefer AMD over Intel - even though I am aware Intel are ahead and outperforming AMD.

This should provide more competition to Intel, which is always good.

L2 cache isn't something that you can just ignore for processors. It's where the instruction stack is located (if I remember correctly), which basically means they won't need to be saved in system memory, increasing the effeciency of the processor greatly.

I'm wondering how much they cost, the bottom line C2Q is ~260 dollars @ 4 x 2.4GHz, and seeing AMD has only three quad core models in the Phenom line (2 x 2.4 and a 2.6 GHz), I doubt they'll have a cheaper model with the same clocking.

Those processors are for servers--not for desktop computers. They'll likely work in the AM2+ boards, which is a pretty good thing for desktop-users. I'll wait for benchmarks... and overclock numbers. AMD is still all talk and no walk.

yep, bob is right. Barcelona is a processor designed for servers. AMD Agena is the one we have to really look out for.

Can someone explain the dyanmics of a quad core processor, and how it works? What is a L2 Cache??

Quad core means four identical cores have been placed on one chip, so they can function as one processor, but with the power of four. The main advantage is that instead of one command at a time, a quad core can handle up to four at a time.

L2 cache is one of the two cache storages of a processor. Every core in a quad core has it's own L1 cache, but the L2 cache is shared by all the cores. Both are used to store requently used locations in the memory, to reduce the time spent on grabbing content from the memory.

About the cache--that's not quite correct.

L1 cache is lowest-level, meaning it stores the code that is being run through during each clock cycle. L2 cache can be a dedicated addition to L1 cache, or it can be a shared addition. In most AMDs, they have a single L2 cache (256KB-512KB) for each processing core. In contrast, in most Intels (since the Pentium D 900s), the L2 cache is a shared cache (1-4MB total) between all the processing cores. However, Intel's current quad-core offerings is a combined case--they have 4MB of L2 cache shared between core#0 and #1, with an additional 4MB of L2 cache shared between core#2 and #3. This makes for a surprisingly good brute-force cache...

Remember, AMDs have on-chip memory controllers. They're much better at using RAM then Intel chips. Intel has made up for this little problem with their current digs--they have brute-force caches that can store more, to make up for the more-limited memory bandwidth. It's a given and accepted fact--nearly every AMD on the market right now will utilize memory better then basically every Intel on the market now.

Last thing--Intel is going to be making its way towards on-die memory controllers, in the Nehalem micro architecture. That'll be based first on a 45nm process and use a different socket (incompatible with all LGA775 chips and boards). They'll probably all be DDR3 memory controllers on the Nehalem chips--though DDR3 should drop in price by the time of launch.

EDIT: Forgot to mention--L3 Cache has been used for some Pentium 4's, some AMD K6-2+'s and K6-III's, and is being reused for the Barcelona evolution of K8. If memory serves, Intel is simply going to be expanding on L2 memory sizes--the Penryn-based Core processors will have 6MB of shared L2 cache for dual-cores and 6-12MB of share L2 cache for quad-cores. Again, if memory serves (too bad it's early on a sunday morning), it's going to be a single L2 cache--not split between core#0-#1 and #2-#3..